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word lines that bracket a common source diffusion In Figure 829, these are referred to as the even and odd word lines associated with a source line Erasing takes place by applying a bias of - 15 V to the word Iines in the erase block while all of the bit lines and the source lines associated with the selected word lines are grounded With the B/Ls and source lines grounded, an inN ersion layer will be formed in the floating gate channel as soon as the floating gate is coupled above its native threshold The capacitances of the floating gate to the inversion layer and the source overlap region dominate the total floating gate capacitance so that most of the applied W/L bias appears across the interpoly oxide.

The poly 1 floating gate is oxidized in a way that encourages the formation of sharp edges along the edge of the poly 1 as shown schematically in Figure 828 The field enhancement along these edges allows tunneling through relatively thick interpoly oxide as discussed with respect to Figure 88 Because the tunneling is interpoly, high voltage is not applied to junctions in the array; hence, there is no band-to-band tunneling The 15-V bias can be generated with a low-power, on-chip charge pump Cells are selectively programmed by applying about 12-V of bias to one of the source lines One of the word lines neighboring the selected source line is biased at ground, which prevents current through cells on that row The other word line is biased slightly above threshold for the drain-select transistors.

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The unselected bit lines are biased at VDD; the bit lines containing the cells to be programmed are grounded, which allows current flow through the cells on the selected row and bit lines The large source underlap diffusion couples the floating gate upward in potential Since the channel of the floating gate transistor is essentially depleted and the interpoly oxide is relatively thick, the source to floating gate coupling ratio (Rs FG = Cs FG/CToT) is high, typically - 80% This means that the 12-V source bias increases the potential on the floating-gate by - 96 V These are the conditions described with reference to Figure 85 fo- efficient source side injection The channel current can be limited by the bias on the 1:oly 2 transistor to < 1 jiA, which allows the 12-V bias to be generated with an on-chip charge pump.

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In the read mode, the source lines are all grounded The selected row line is biased at a voltage that turns on the select transistor, for example, VDD, and the selected bit lines are biased at - 2 V Those cells that are programmed don't conduct while those that are erased conduct Note that because of the existence of the drain select gate, the cells may be erased into depletion as indicated in Figure 813a, which is advantageous for reading under low supply voltage conditions Triple-Poly, Virtual Ground (TPVG) Flash Cell The TPVG flash also utilizes hot-electron injection for programming and FN tunneling for erase as do the two flash 2els discussed previously, but differs from each of these cells in two important ways.

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This approach (1) employs a virtual ground and (2) uses CHE injection for programming and geometrically enhanced tunneling for erase, so that it differs from each of the two previous approaches in one of the write modes A layout view and cross-sectional drawings through the cell along the channel A-A' and across the channel of the TPVG cell are shown in Figure 83054,5 This.

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